Construction of Arithmetic Processor (AP)
Each AP consists of a 4-way super-scalar unit (SU), a vector
unit (VU), and main memory access control unit on a single LSI
chip. The AP operates at a clock frequency of 500MHz with some
circuits operating at 1GHz. Each SU is a super-scalar processor
with 64KB instruction caches, 64KB data caches, and 128 general-purpose
scalar registers. Branch prediction, data prefetching and out-of-order
instruction execution are all employed. Each VU has 72 vector
registers, each of which has 256 vector elements, along with
8 sets of six different types of vector pipelines: addition/shifting,
multiplication, division, logical operations, masking, and load/store.
The same type of vector pipelines works together by a single
vector instruction and pipelines of different types can operate
concurrently. The VU and SU support the IEEE 754 floating-point
data format.
1 Chip LSI : 8Gflops
- 0.15µm CMOS
- 8Layers copper interconnection
- 20.79mm x 20.79mm
- 60 million transistors
- 5185 pins
- Clock Cycle: 500MHz(1GHz)
- Power Consumption: 140W (Typ.)
Package of Arithmetic Processor (AP)
